Flip flop circuit

ABSTRACT

A flip-flop circuit includes a first latch, a second latch, and a trigger stage. The first latch is configured to set a first latch output signal based on a first latch input signal and a clock signal. The second latch is configured to set a second latch output signal based on a second latch input signal and the clock signal. The trigger stage is configured to generate the second latch input signal based on the first latch output signal. The trigger stage is configured to cause the second input signal to have different voltage swings based on the first latch output signal and the second latch output signal.

CROSS-REFERENCE

The present application relates to U.S. patent application Ser. No. 14/472,937, filed on Aug. 29, 2014, titled “FLIP FLOP CIRCUIT,” and the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

In silicon-on-chip (SOC) designs, flip-flop circuits such as D-type flip-flops (DFFs) or scan DFFs (SDFFs and also referred to as scan flip-flops) are used to perform desired functions of a circuit design. For example, scan chains that comprise a plurality of interconnected scan flip-flops are used to obtain access to internal nodes of an integrated circuit (IC) to simplify testing of the IC by passing test data through the scan flip-flops. The scan flip-flop is configured to operate in one of two modes, data mode and scan mode. When a scan enable signal (assumed active high) of a scan flip-flop is set to a low logical value, the scan flip-flop is in the data mode. When the scan enable signal of the scan flip-flop is set to a high logical value, the scan flip-flop is in scan mode. For a full scan design, during scan testing, all of the flip-flops and all of the combinational logic connected to the flip-flops, may be toggling at the same time, causing relatively high power consumption. This high power consumption may exceed the circuit's power rating as IC chip density and speed increase.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a circuit diagram of a flip-flop circuit in accordance with some embodiments.

FIG. 2 is a timing diagram of signals at various nodes of the flip-flop circuit in FIG. 1 in accordance with some embodiments.

FIG. 3A is a circuit diagram of an example AND-OR-INV circuit in accordance with some embodiments.

FIG. 3B is a circuit diagram of an example circuit usable as an input stage of the flip-flop circuit in FIG. 1 in accordance with some embodiments.

FIG. 4A is a circuit diagram of an example OR-AND-INV circuit in accordance with some embodiments.

FIG. 4B is a circuit diagram of another example OR-AND-INV circuit in accordance with some embodiments.

FIG. 5 is a circuit diagram of an example circuit usable as a trigger stage of the flip-flop circuit in FIG. 1 in accordance with some embodiments.

FIGS. 6A-6D are circuit diagrams of example circuits usable as a voltage setting circuit of the flip-flop circuit in FIG. 1 in accordance with some embodiments.

FIG. 7 is a flow chart of a method of operating a flip-flop circuit in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In some embodiments, a flip-flop circuit includes a trigger stage that is configured to set an output signal of the trigger stage to have two different voltage swings responsive to a stored value of the flip-flop circuit. Compared with a counterpart flip-flop circuit that does not adjust the voltage swing of the output signal of the trigger stage, the flip-flop circuit according to the present application consumes less power when more transistors are subject to be toggled responsive to a clock signal.

FIG. 1 is a circuit diagram of a flip-flop circuit 100 in accordance with some embodiments. Flip-flop circuit 100 includes an input stage 110, a first latch 120 coupled with input stage 110, a second latch 130, and a trigger stage 140 coupled with the first latch 120 and the second latch 130.

Input stage 110 is configured to select one of a plurality of input signals, such as a scan input signal SI or a data input signal D, in response to a scan enable signal SE and output a signal M for first latch 120 based on the selected signal. Input stage 110 includes an inverter N1, two AND gates A1 and A2, and an OR gate O1. Inverter N1 receives signal SE and output signal /SE, which is logically complementary to signal SE. AND gate A1 includes a first input 102 a, a second input 102 b, and an output 102 c. The first input 102 a of AND gate A1 receives signal SI, and the second input 102 b of AND gate A1 receives signal SE. AND gate A2 includes a first input 104 a, a second input 104 b, and an output 104 c. The first input 104 a of AND gate A2 receives signal /SE, and the second input 104 b of AND gate A2 receives signal D. OR gate O1 includes a first input 106 a, a second input 106 b, and an output 106 c. The first input 106 a of OR gate O1 is coupled with the output 102 c of AND gate A1, and the second input 106 b of OR gate O1 is coupled with the output 104 c of AND gate A2. The output 106 c of OR gate O1 is coupled with first latch 120.

When the flip flop 100 is operated in a first mode, signal SE is set to have a high logical value. AND gate A2 outputs a low logical value, irrespective of the logic state of signal D. The output 106 c of OR gate O1 thus depends on signal SI. When signal SI is logically high, the output 106 c of OR gate O1 is also logically high. When signal SI is logically low, the output 106 c of OR gate O1 is also logically low. As a result, when signal SE is logically high, signal M has a logical state the same as that of signal SI.

When the flip flop 100 is operated in a second mode, signal SE is set to have a low logical value. AND gate A1 outputs a low logical value, irrespective of the logic state of signal SI. The output 106 c of OR gate O1 thus depends on signal D. When signal D is logically high, the output 106 c of OR gate O1 is also logically high. When signal D is logically low, the output 106 c of OR gate O1 is also logically low. As a result, when signal SE is logically low, signal M has a logical state the same as that of signal D.

In the present embodiment, the flip-flop circuit 100 is usable as a scan flip-flop, where the first mode is also referred to as a “scan mode” and the second mode is also referred to as a “data mode.” In some embodiments, the flip-flop circuit 100 is usable as a non-scan flip-flop, where input stage 110 is omitted, and data input signal D is directly fed to node M.

First latch 120 is configured to set a first latch output signal X based on signal M (also referred to as “first latch input signal”) and a clock signal CP. The first latch 120 updates a logical state of the first latch output signal X based on the first latch input signal M in response to a first state of clock signal CP and holds the logical state of the first latch output signal X in response to a second state of clock signal CP. In some embodiments, the first state and the second state of clock signal CP are logically complementary to each other. In some embodiments, the first state of clock signal CP refers to a low logical value, and the second state of clock signal CP refers to a high logical value.

First latch 120 includes two AND gates A3 and A4, a NOR gate NR1, and an inverter N2. AND gate A3 includes a first input 122 a, a second input 122 b, and an output 122 c. The first input 122 a of AND gate A3 is coupled with trigger stage 140. The second input 122 b of AND gate A3 is coupled with the output 106 c of OR gate O1 and configured to receive signal M. AND gate A4 includes a first input 124 a, a second input 124 b, and an output 124 c. The first input 124 a of AND gate A4 is configured to receive clock signal CP. NOR gate NR1 includes a first input 126 a, a second input 126 b, and an output 126 c. The first input 126 a of NOR gate NR1 is coupled with the output 122 c of AND gate A3. The second input 126 b of NOR gate NR1 is coupled with the output 124 c of AND gate A4. The output 126 c of NOR gate NR1 is coupled with the trigger stage 140 and carries signal X. Inverter N2 has an input 128 a and an output 128 c. The input 128 a of inverter N2 is coupled with the output 126 c of NOR gate NR1, and the output 128 c of inverter N2 is coupled with the second input 124 b of AND gate A4.

Second latch 130 is configured to set a second latch output signal QN based on a signal TR (also referred to as “second latch input signal”) and clock signal CP. Second latch 130 is also configured to output a signal Q based on signal QN. The second latch 130 updates a logical state of the second latch output signal QN based on the second latch input signal TR in response to the second state of clock signal CP and holds the logical state of the second latch output signal QN in response to the first state of clock signal CP.

Second latch 120 includes an OR gate O2, a NAND gate ND1, and two inverters N3 and N4. OR gate O2 includes a first input 132 a, a second input 132 b, and an output 132 c. The second input 132 b of OR gate O2 is configured to receive clock signal CP. NAND gate ND1 includes a first input 134 a, a second input 134 b, and an output 134 c. The first input 134 a of NAND gate ND1 is coupled with the output 132 c of OR gate O2. The second input 134 b of NAND gate ND1 is configured to receive signal TR. The output 134 c of NAND gate ND1 carries signal QN. Inverter N3 has an input 136 a and an output 136 c. The input 136 a of inverter N3 is coupled with the output 134 c of NAND gate ND1, and the output 136 c of inverter N3 is coupled with the first input 132 a of OR gate O2. Inverter N4 has an input 138 a and an output 138 c. The input 138 a of inverter N4 is coupled with the output 134 c of NAND gate ND1, and the output 138 c of inverter N4 carries signal Q.

Trigger stage 140 is configured to generate second latch input signal TR based on clock signal CP, first latch output signal X, and second latch output signal QN. Trigger stage 140 is also configured to cause second input signal TR to have two different voltage swings based on second latch output signal QN. In some embodiments, second input signal TR has a first voltage swing in response to a first state of second latch output signal QN and a second voltage swing in response to a second state of second latch output signal QN, where the second voltage swing is less than the first voltage swing. In some embodiments, the first state of signal QN refers to a low logical value, and the second state of signal QN refers to a high logical value. In some embodiments, a high voltage level and a low voltage level of the second voltage swing are still recognizable by AND gate A3 and NAND gate ND1 as corresponding to the high logical value and the low logical value, respectively.

Trigger stage 140 includes a NAND gate ND2 and a voltage setting circuit VS. NAND gate ND2 includes a first input 142 a, a second input 142 b, an output 142 c, and a adjustable power node 142 d. The first input 142 a of NAND gate ND2 is configured to receive clock signal CP. The second input 142 b of NAND gate ND2 is coupled with the output 126 c of NOR gate NR1 and configured to receive signal X. The output 142 c of NAND gate ND2 carries signal TR. Voltage setting circuit VC includes an input node 144 a and an output node 144 c. The input node 144 a of voltage setting circuit VC is coupled with output node 134 c of NAND gate ND1 and configured to receive signal QN. The output node of voltage setting circuit VC is coupled with adjustable power node 142 d of NAND gate ND2.

In some embodiments, voltage setting circuit VC sets a voltage at the output node 144 c of the voltage setting circuit VC to have a first power supply voltage level in response to the first state of signal QN and a second power supply voltage level in response to the second state of signal QN. In some embodiments, the second power supply voltage level is less than the first power supply voltage level.

In operation, NAND gate ND2 sets signal TR at a high logical value when clock signal has a low logical value and sets signal TR to have the logical value complementary to that of signal X when clock signal has a high logical value. In some embodiments, the high logical value of TR corresponds to the first power supply voltage level when signal X has a low logical value regardless the logical state of signal QN; and the high logical value of TR corresponds to the second power supply voltage level when signal X has a high logical value and signal QN has a low logical value.

With respect to first latch 120, inverter N2 set signal XB to be logically complementary to signal X (i.e., “/X”). When clock signal CP is logically low, signal TR is logically high. As such, AND gate A4 outputs a low logical value and AND gate A3 outputs a logical value the same as that of signal M. NOR gate NR1 thus sets signal X to have a logical value complementary to the logical value of signal M. On the other hand, when clock signal CP is logically high, signal TR has a logical value complementary to that of signal X and the same as that of signal XB. As such, AND gate A4 outputs a logical value the same as that of signal XB and AND gate A3 outputs either the low logical value or a logical value the same as that of signal XB. NOR gate NR1 thus sets signal X to have a logical value complementary to the logical value of signal XB.

With respect to second latch 130, inverter N3 sets signal QNB to be logically complementary to signal QN (i.e., “/QN”), and inverter N4 sets signal Q to be logically complementary to signal QN. When clock signal CP is logically high, signal TR has a logical value complementary to that of signal X. As such, OR gate O2 outputs the high logical value. NAND gate ND1 thus sets signal QN to have a logical value complementary to the logical value of signal TR. On the other hand, when clock signal CP is logically low, signal TR is logically high. As such, OR gate O2 outputs a logical value the same as that of signal QNB. NAND gate ND1 thus sets signal QN to have a logical value complementary to the logical value of signal QNB.

Operation of flip-flop circuit 100 is summarized in Table 1 below.

TABLE 1 CP TR /X (or XB) /QN (or Q) LOW HIGH M (update) the previously stored value (hold) HIGH /X (updated the previously TR (update) based on M stored value when CP = (hold) LOW)

As presented in Table 1, when signal M remains logically low for a plurality of clock cycles of clock signal CP, signal QN remains logically high and signal X remains logically high. However, signal TR is logically high when clock signal CP is logically low and signal TR is logically low when clock signal CP is logically high. As a result, transistors of NAND gate ND1 and AND gate A3 are being toggled although the logical values of signals M, X, and Q remain unchanged. Under this scenario, voltage setting circuit VS sets the signal TR to have a lowered voltage swing in response to the high logical value of signal QN when signal X has a logical high value, and the power consumption of trigger stage 140 is thus reduced. Compared with a configuration in which signal TR does not have the lowered voltage swing, when signal QN is logically high and signal X has a logical high value, flip-flop circuit 100 consumes about 20% to 30% less power.

FIG. 2 is a timing diagram of signals at various nodes of the flip-flop circuit 100 in FIG. 1 in accordance with some embodiments. The elements of FIG. 1 are being used in conjunction with the waveforms in FIG. 2 for explaining the operation of flip-flop circuit 100. A voltage level VDD corresponds to the high logical value, and a voltage level VSS corresponds to the low voltage value. In the embodiment depicted in FIG. 2, voltage setting circuit VS is capable of setting signal TR to have a first voltage swing between voltage levels VDD and VSS or a second voltage swing between voltage levels VDD′ and VSS. A voltage difference AV is between voltage level of VDD and voltage level VDD′. In some embodiments, voltage difference AV is set to be recognizable by AND gate A3 and NAND gate ND1 as corresponding to the high logical value.

At time T1, clock signal CP is logically low and signal TR is kept logically high due to the first state of clock signal CP, irrespective of the state of signal X. Signal M transitions from logically high to logically low based on signal D or signal SI. The output of first latch 120, signal X, is set to logically high based on signal TR, signal M, clock signal CP, and signal XB. Moreover, signal QN is kept at a currently stored value, assumed low.

At time T2, clock signal CP transitions from logically low to logically high. Signal X is already set to be logically high, and signal XB is thus pulled to logically low due to the logically high signal X. Signal TR, based on clock signal CP and signal X, is caused to be subsequently pulled low after time T2.

At time T3, signal TR transitions to logically low due to the logically high signals CP and X. Meanwhile, with signals TR and XB at logically low, signal X is held at the previously stored value (e.g., logically high), irrespective of the state of signal M. Furthermore, with signal TR pulled low, signal QN is subsequently pulled high after time T3. Voltage setting circuit VS is set to provide a reduced voltage level VDD′ to NAND ND2.

Next, at time T4, clock signal CP transitions from high to low. At time T5, in response to the low logical value of clock signal CP and high logical value of signal X, signal TR is set to logically high, irrespective of the state of signal X. Because voltage setting circuit VS has been set to provide the reduced voltage level VDD′ to NAND ND2, signal TR is pulled to the reduced voltage level VDD′ rather than voltage level VDD.

Prior to time T6, signal M is set to logically low as the signal M from the previous cycle (i.e., at time T1). The output of first latch 120, signal X, remains at logically high and signal QN remains at a currently stored value, e.g., logically high.

At time T7, clock signal CP transitions to logically high. Signal X remains at logically high and signal XB remains at logically low. Trigger signal TR, based on clock signal CP and signal X, is caused to be subsequently pulled low after time T7. At time T8, clock signal CP transitions from high to low. At time T9, signal TR transitions to logically high due to the logically low signal CP and the logically high signal X. Signal QN remains at logically high. Because signal QN is still logically high, voltage setting circuit VS is still set to provide the reduced voltage level VDD′ to NAND ND2, and signal TR is pulled to the reduced voltage level VDD′ rather than voltage level VDD.

A time T10, signal M is set to logically high based on signal D or signal SI, which carries a different value than signal M at time period T1-T3 and T5-T7. The output of first latch 120, signal X, is set to logically low based on signal TR, signal M, clock signal CP, and signal XB. Meanwhile, signal QN is set at a currently stored value, which is logically high. At time T11, because signal X has a logical high value, signal TR is set to voltage level VDD regardless the state of signal QN.

At time T12, clock signal CP transitions to logically high. Signal X is already set to be logically low, and signal XB is thus pulled to logically high due to the logically low signal X. Signal TR, based on clock signal CP and signal X, remains at logically high after time T11. Because signal X has a logical low value, signal TR remains at the voltage level VDD.

At time T13, with signals TR and XB at logically high, signal X is held at the previously stored value (e.g., logically low), irrespective of the state of signal M. Furthermore, with signal TR at logically high, signal QN is pulled low at time T13. Voltage setting circuit VS is thus set to provide the voltage level VDD to the adjustable power node 142 d of NAND ND2 rather than the reduced voltage level VDD′. Because signal X has a logical low value, signal TR remains at the voltage level VDD.

FIG. 3A is a circuit diagram of an example AND-OR-INV (AOI) circuit 300A in accordance with some embodiments. AOI circuit 300A is usable as a compound logical gate for implementing AND gates A3 and A4 and NOR gate NR1. AOI circuit 300A has a first input 302 a, a second input 302 b, a third input 304 a, a fourth input 304 b, and an output 306 c. In some embodiments, first input 302 a corresponds to input 122 a in FIG. 1; second input 302 b corresponds to input 122 b, third input 304 a corresponds to input 124 a, fourth input 304 b corresponds to input 124 b, and output 306 c corresponds to output 126 c.

AOI circuit 300A includes P-type transistors 312, 314, 316, and 318, and N-type transistors 322, 324, 326, and 328. P-type transistor 312 has a source coupled with a power supply node 332 configured to carry a power supply voltage having voltage level VDD. P-type transistor 312 has a drain coupled with a source of P-type transistor 314. P-type transistor 314 further has a drain coupled with output 306 c. P-type transistor 316 has a source coupled with power supply node 332 and a drain coupled with a source of P-type transistor 318. P-type transistor 318 further has a drain coupled with output 306 c. Drains of P-type transistor 312 and 316 are coupled together.

N-type transistor 324 has a source coupled with another power supply node 334 configured to carry a reference voltage having voltage level VSS. N-type transistor 324 has a drain coupled with a source of N-type transistor 322. N-type transistor 322 further has a drain coupled with output 306 c. N-type transistor 328 has a source coupled with power supply node 334 and a drain coupled with a source of N-type transistor 326 N-type transistor 326 further has a drain coupled with output 306 c.

Moreover, gates of transistors 318 and 324 are coupled with input 302 a; gates of transistors 314 and 322 are coupled with input 302 b; gates of transistors 312 and 328 are coupled with input 304 a; and gates of transistors 316 and 326 are coupled with input 304 b. In some embodiments, the configuration for nodes 302 a and 302 b are interchangeable. In some embodiments, the configuration for nodes 304 a and 304 b are interchangeable.

FIG. 3B is a circuit diagram of an example circuit 300B usable in an input stage 110 of the flip-flop circuit in FIG. 1 in accordance with some embodiments. Circuit 300B is usable as a compound logical gate for implementing AND gates A1 and A2 and OR gate O1. Circuit 300B has a first input 342 a, a second input 342 b, a third input 344 a, a fourth input 344 b, and an output 346 c. In some embodiments, first input 342 a corresponds to input 102 a in FIG. 1; second input 342 b corresponds to input 102 b, third input 344 a corresponds to input 104 a, fourth input 344 b corresponds to input 104 b, and output 346 c corresponds to output 106 c.

Circuit 300B includes an AOI circuit 350 and an inverter 360. AOI circuit 350 corresponds to AOI circuit 300 A and has a first input 352 a, a second input 352 b, a third input 354 a, a fourth input 354 b, and an output 356 c. First input 352 a corresponds to input 302 a; second input 352 b corresponds to input 302 b; third input 354 a corresponds to input 304 a; and fourth input 354 b corresponds to input 304 b. First input 352 a is usable as input 342 a; second input 352 b is usable as input 342 b; third input 354 a is usable as input 344 a; and fourth input 354 b is usable as input 344 b.

Inverter 360 has an input 362 a coupled with output 356 c of AOI circuit 350. Inverter also has an output 362 c usable as output 346 c of circuit 300B.

FIG. 4A is a circuit diagram of an example OR-AND-INV (OAI) circuit 400A in accordance with some embodiments. OAI circuit 400A is usable as a compound logical gate 400 for implementing OR gate O2 and NAND gate ND1 in FIG. 1. OAI gate 400 has a first input 402 a, a second input 402 b, a third input 404 b, and an output 406 c. In some embodiments, first input 402 a corresponds to input 132 a in FIG. 1; second input 402 b corresponds to input 132 b, third input 404 b corresponds to input 134 b, and output 406 c corresponds to output 134 c.

OAI circuit 400A includes P-type transistors 412, 414, and 416, and N-type transistors 422, 424, and 426. P-type transistor 412 has a source coupled with a power supply node 432 configured to carry a power supply voltage having voltage level VDD. P-type transistor 412 has a drain coupled with a source of P-type transistor 414. P-type transistor 414 further has a drain coupled with output 406 c. P-type transistor 416 has a source coupled with power supply node 432 and a drain coupled with output 406 c.

N-type transistor 424 has a source coupled with another power supply node 434 configured to carry a reference voltage having voltage level VSS. N-type transistor 424 has a drain coupled with a source of N-type transistor 422. N-type transistor 422 further has a drain coupled with output 406 c. N-type transistor 426 has a source coupled with the drain of N-type transistor 424. N-type transistor 426 has a drain coupled with output 406 c.

Moreover, gates of transistors 412 and 426 are coupled with input 402 a; gates of transistors 414 and 422 are coupled with input 402 b; and gates of transistors 416 and 424 are coupled with input 404 b. In some embodiments, the configuration for nodes 402 a and 402 b are interchangeable.

FIG. 4B is a circuit diagram of another example OR-AND-INV circuit 400B in accordance with some embodiments. OAI circuit 400B is also usable as a compound logical gate 400 for implementing OR gate O2 and NAND gate ND1 in FIG. 1. OAI circuit 400B includes P-type transistors 442, 444, and 446, and N-type transistors 452, 454, and 456. P-type transistor 442 has a source coupled with power supply node 432 and a drain coupled with a source of P-type transistor 444. P-type transistor 444 further has a drain coupled with output 406 c. P-type transistor 446 has a source coupled with power supply node 332 and a drain coupled with output 406 c.

N-type transistor 454 has a source coupled with power supply node 434 and a drain coupled with a source of N-type transistor 452. N-type transistor 454 further has a drain coupled with output 406 c. N-type transistor 456 has a source coupled with power supply node 334 and a drain coupled with the drain of N-type transistor 454.

Moreover, gates of transistors 442 and 456 are coupled with input 402 a; gates of transistors 444 and 454 are coupled with input 402 b; and gates of transistors 446 and 452 are coupled with input 404 b. In some embodiments, the configuration for nodes 402 a and 402 b are interchangeable.

FIG. 5 is a circuit diagram of an example circuit 500 usable as a trigger stage 140 of the flip-flop circuit in FIG. 1 in accordance with some embodiments. Circuit 500 includes a voltage setting circuit 510 and a NAND gate 520. Voltage setting circuit 510 is usable as voltage setting circuit VS in FIG. 1, and NAND gate 520 is usable as NAND gate ND2.

Voltage setting circuit 510 includes an input node 512 a and an output node 512 c. In some embodiments, input node 512 a is configured to receive signal QN from second latch 130. Voltage setting circuit 510 is configured to set a voltage at the output node 512 c to have a first power supply voltage level, such as voltage level VDD, in response to the logically low state of signal QN at node 512 a and to have a second power supply voltage level, such as voltage level VDD′, in response to the logically high state of signal QN. Various implementations of voltage setting circuit will be further illustrated in conjunction with FIGS. 6A-6D.

NAND gate 520 includes inputs 522 a and 522 b, an output 522 c, and a adjustable power node 522 d. Power node 522 d corresponds to adjustable power node 142 d in FIG. 1 and is coupled with output node 512 c of voltage setting circuit 510. Input 522 a corresponds to input 142 a; input 522 b corresponds to input 142 b; and output 522 c corresponds to output 142 c.

NAND gate 520 includes P-type transistors 524 and 525 and N-type transistors 528 and 529. P-type transistor 524 includes a source coupled with the power node 522 d and a drain coupled with output 522 c. P-type transistor 525 includes a source coupled with a power supply node 532 configured to carry a power supply voltage having voltage level VDD. P-type transistor 525 also includes a drain coupled with output 522 c. N-type transistor 529 includes a source coupled with another power supply node 534 configured to carry a reference voltage having voltage level VSS. N-type transistor 529 also includes a drain coupled with a source of N-type transistor 528. N-type transistor 528 further includes a drain coupled with output 522 c.

Moreover, gates of transistors 524 and 528 are coupled with input 522 a; and gates of transistors 525 and 529 are coupled with input 522 b.

FIG. 6A is a circuit diagrams of an example circuit 600A usable as a voltage setting circuit VS of the flip-flop circuit in FIG. 1 or voltage setting circuit 510 in FIG. 5 in accordance with some embodiments.

Circuit 600A includes an input node 602 a, an output node 602 c, a power node 604 configured to carry a supply voltage having the power supply voltage level VDD, a P-type transistor 612, and an N-type transistor 614. In some embodiments, input node 602 a corresponds to input node 512 a in FIG. 5, output node 602 c corresponds to output node 512 c, and power node 604 corresponds to power supply node 532.

P-type transistor 612 includes a source coupled with power node 604 and a drain coupled with output node 602 c. N-type transistor 614 includes a drain coupled with power node 604 and a source coupled with output node 602 c. Gates of transistors 612 and 614 are coupled with input node 602 a and are configured to receive a signal QN from second latch 130.

In operation, when signal QN at node 602 a is logically low, transistor 612 is turned on and transistor 614 is turned off. Node 604 and node 602 c are thus electrically coupled together, and node 602 c output a voltage having a voltage level of VDD. When signal QN at node 602 a is logically high, transistor 612 is turned off and transistor 614 is turned on. Node 602 c is forced by N-type transistor 614 to have a voltage level of VDD-Vthn, where Vthn is the threshold voltage of N-type transistor 614. In some embodiments, the voltage level of VDD-Vthn is set to be still recognizable by AND gate A3 and NAND gate ND1 as corresponding to the high logical value.

FIG. 6B is a circuit diagrams of another example circuit 600B usable as a voltage setting circuit VS of the flip-flop circuit in FIG. 1 or voltage setting circuit 510 in FIG. 5 in accordance with some embodiments. Components that are the same or similar to those in FIG. 6A are given the same reference numbers, and detailed description thereof is omitted.

Circuit 600B includes input node 602 a, output node 602 c, power node 604, and P-type transistors 632 and 634. P-type transistor 632 includes a source coupled with power node 604, a drain coupled with output node 602 c, and a gate coupled with input node 602 a and is configured to receive a signal QN from second latch 130. P-type transistor 634 includes a source coupled with power node 604, a drain coupled with output node 602 c, and a gate coupled with output node 602 c. Therefore, P-type transistor 634 is a diode-connected transistor having an anode coupled with power node 604 and a cathode coupled with output node 602 c.

In operation, when signal QN at node 602 a is logically low, transistor 632 is turned on. Node 604 and node 602 c are thus electrically coupled together through transistor 632, and node 602 c output a voltage having a voltage level of VDD. When signal QN at node 602 a is logically high, transistor 632 is turned off. Node 602 c is forced by the diode-connected transistor 634 to have a voltage level of VDD-Vthp, where Vthp is the threshold voltage of P-type transistor 634. In some embodiments, the voltage level of VDD-Vthp is set to be still recognizable by AND gate A3 and NAND gate ND1 as corresponding to the high logical value.

FIG. 6C is a circuit diagrams of another example circuit 600C usable as a voltage setting circuit VS of the flip-flop circuit in FIG. 1 or voltage setting circuit 510 in FIG. 5 in accordance with some embodiments. Components that are the same or similar to those in FIG. 6A are given the same reference numbers, and detailed description thereof is omitted.

Circuit 600C includes input node 602 a, output node 602 c, power node 604, a P-type transistor 642, and an N-type transistor 644. P-type transistor 642 includes a source coupled with power node 604, a drain coupled with output node 602 c, and a gate coupled with input node 602 a and is configured to receive a signal QN from second latch 130. N-type transistor 644 includes a drain coupled with power node 604, a source coupled with output node 602 c, and a gate coupled with power node 604. Therefore, N-type transistor 644 is a diode-connected transistor having an anode coupled with power node 604 and a cathode coupled with output node 602 c.

In operation, when signal QN at node 602 a is logically low, transistor 642 is turned on. Node 604 and node 602 c are thus electrically coupled together through transistor 642, and node 602 c output a voltage having a voltage level of VDD. When signal QN at node 602 a is logically high, transistor 642 is turned off. Node 602 c is forced by the diode-connected transistor 644 to have a voltage level of VDD-Vthn, where Vthn is the threshold voltage of N-type transistor 644. In some embodiments, the voltage level of VDD-Vthn is set to be still recognizable by AND gate A3 and NAND gate ND1 as corresponding to the high logical value.

FIG. 6D is a circuit diagrams of another example circuit 600D usable as a voltage setting circuit VS of the flip-flop circuit in FIG. 1 or voltage setting circuit 510 in FIG. 5 in accordance with some embodiments. Components that are the same or similar to those in FIG. 6A are given the same reference numbers, and detailed description thereof is omitted.

Circuit 600D includes an input node 602 a, an output node 602 c, a first power node 604 configured to carry a supply voltage having the power supply voltage level VDD, and a second power node 606 configured to carry a supply voltage having the power supply voltage level VDD′. Circuit 600D further includes P-type transistors 652 and 654 and an inverter 662.

Inverter 662 includes an input and an output. The input of inverter 662 is coupled with input node 602 a and is configured to receive a signal QN from second latch 130. The output of inverter 662 thus generates a signal /QN logically complementary to signal QN. P-type transistor 652 includes a source coupled with power node 604, a drain coupled with output node 602 c, and a gate coupled with input node 602 a. P-type transistor 654 includes a source coupled with power node 606, a drain coupled with output node 602 c, and a gate coupled with the output of inverter 662. In some embodiments, P-type transistors 652 and 654 are replaced by other type of switching devices, such as other types of transistors or transmission gates.

In operation, when signal QN at node 602 a is logically low, transistor 652 is turned on and transistor 654 is turned off. Node 604 and node 602 c are thus electrically coupled together, and node 602 c output a voltage having a voltage level of VDD. When signal QN at node 602 a is logically high, transistor 652 is turned off and transistor 654 is turned on. Node 606 and node 602 c are thus electrically coupled together, and node 602 c output a voltage having a voltage level of VDD′. In some embodiments, the voltage level of VDD′ is set to be still recognizable by AND gate A3 and NAND gate ND1 as corresponding to the high logical value.

FIG. 7 is a flow chart of a method 700 of operating a flip-flop circuit, such as flip-flop circuit 100 in FIG. 1, in accordance with some embodiments. It is understood that additional operations may be performed before, during, and/or after the method 700 depicted in FIG. 7, and that some other processes may only be briefly described herein.

The method 700 begins with operation 710, where a first latch 120 of flip-flop circuit 100 sets a signal X based on signal M and in response to a clock signal CP. Then, in operation 720, a signal TR is generated by a trigger circuit, such as trigger stage 140, based on signal X, the clock signal CP, and a signal QN from a second latch 130. Finally, in operation 730, the second latch 130 sets signal QN based on signal TR and in response to the clock signal CP.

In some embodiments, operation 710 includes updating a logical state of signal X based on signal M in response to a low logical state of clock signal CP and holding the logical state of signal X in response to a high logical state of clock signal CP. In some embodiments, operation 730 includes updating a logical state of signal QN based on signal TR in response to the high logical state of clock signal CP and holding the logical state of signal QN in response to the low logical state of clock signal CP.

Moreover, operation 720 includes performing operation 722 and operation 726. In operation 722, trigger circuit 140 is set to cause signal TR to have a first voltage swing in response to a low logical state of signal QN. In operation 726, trigger circuit 140 is set to cause signal TR to have a second voltage swing in response to a high logical state of signal QN. In some embodiments, the second voltage swing is less than the first voltage swing. In some embodiments, operation 722 includes setting a voltage at an output node of a voltage setting circuit VC of the trigger circuit 140 to have a first power supply voltage level VDD in response to the first state of signal QN. In some embodiments, operation 726 includes setting a voltage at an output node of a voltage setting circuit VC of the trigger circuit 140 to have a second power supply voltage level VDD′ in response to the second state of signal QN, where the second power supply voltage level VDD′ is less than the first power supply voltage level VDD.

In accordance with one embodiment, a flip-flop circuit includes a first latch, a second latch, and a trigger stage. The first latch is configured to set a first latch output signal based on a first latch input signal and a clock signal. The second latch is configured to set a second latch output signal based on a second latch input signal and the clock signal. The trigger stage is coupled with the first latch and the second latch. The trigger stage is configured to generate the second latch input signal based on the first latch output signal. The trigger stage is configured to cause the second input signal to have different voltage swings based on the first latch output signal and the second latch output signal.

In accordance with another embodiment, a flip-flop circuit includes a first latch, a second latch, and a trigger stage. The first latch is configured to, based on a first signal and in response to a clock signal, generate a second signal. The trigger stage is coupled with the first latch and configured to generate a third signal based on the clock signal, the second signal, and a fourth signal. The second latch is coupled with the trigger stage and configured to, based on the third signal and in response to the clock signal, generate the fourth signal. The trigger stage includes a voltage setting circuit. The voltage setting circuit includes an output node and is configured to set a voltage at the output node of the voltage setting circuit in response to the fourth signal.

In accordance with another embodiment, a method of operating a flip-flop circuit is disclosed. The method includes setting, by a first latch of the flip-flop circuit based on a first signal and in response to a clock signal, a second signal; setting, by a second latch of the flip-flop circuit based on a third signal by and in response to the clock signal, a fourth signal; and generating the third signal by a trigger circuit based on the second signal. The generating the third signal includes setting the trigger circuit to cause the third signal to have different voltage swings based on the fourth signal and the second signal.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A flip-flop circuit, comprising: a first latch configured to set a first latch output signal based on a first latch input signal and a clock signal; a second latch configured to set a second latch output signal based on a second latch input signal and the clock signal; and a trigger stage coupled with the first latch and the second latch, the trigger stage being configured to generate the second latch input signal based on the first latch output signal, the trigger stage being configured to cause the second latch input signal to have different voltage swings based on the first latch output signal and the second latch output signal.
 2. The flip-flop circuit of claim 1, wherein the trigger stage is configured to cause the second latch input signal to have a first voltage swing in response to a first state of the second latch output signal and a second voltage swing in response to a second state of the second latch output signal and a first state of the first latch output signal, the second voltage swing being less than the first voltage swing.
 3. The flip-flop circuit of claim 2, wherein the second voltage swing is greater than a threshold voltage of an N-type transistor of the first latch or greater than a threshold voltage of an N-type transistor of the second latch.
 4. The flip-flop circuit of claim 1, wherein the trigger stage comprises: a voltage setting circuit comprising an output node and configured to set a voltage at the output node of the voltage setting circuit to have a first power supply voltage level in response to the first state of the second latch output signal and a second power supply voltage level in response to the second state of the second latch output signal, the second power supply voltage level being less than the first power supply voltage level; and a NAND gate comprising a first P-type transistor, a source of the first P-type transistor of the NAND gate being coupled with the output node of the voltage setting circuit.
 5. The flip-flop circuit of claim 4, wherein the voltage setting circuit further comprises: a power node configured to carry a first supply voltage having the first power supply voltage level; a P-type transistor having a source coupled with the power node, a gate configured to receive the second latch output signal, and a drain coupled with the output node of the voltage setting circuit; and an N-type transistor having a drain coupled with the power node, a gate configured to receive the second latch output signal, and a source coupled with the output node of the voltage setting circuit.
 6. The flip-flop circuit of claim 4, wherein the voltage setting circuit further comprises: a power node configured to carry a first supply voltage having the first power supply voltage level; a P-type transistor having a source coupled with the power node, a gate configured to receive the second latch output signal, and a drain coupled with the output node of the voltage setting circuit; and a diode having an anode coupled with the power node and a cathode coupled with the output node of the voltage setting circuit.
 7. The flip-flop circuit of claim 4, wherein the voltage setting circuit further comprises: a first power node configured to carry a first supply voltage having the first power supply voltage level; a second power node configured to carry a second supply voltage having the second power supply voltage level; a first switching device configured to electrically couple the first power node to the output node of the voltage setting circuit in response to the first state of the second latch output signal and to electrically decouple the first power node from the output node of the voltage setting circuit in response to the second state of the second latch output signal; and a second switching device configured to electrically couple the second power node to the output node of the voltage setting circuit in response to the second state of the second latch output signal and to electrically decouple the second power node from the output node of the voltage setting circuit in response to the first state of the second latch output signal.
 8. The flip-flop circuit of claim 4, wherein the NAND gate further comprises: a second P-type transistor comprising: a drain coupled with a drain of the first P-type transistor; and a gate configured to receive the first latch output signal; a first N-type transistor comprising a drain coupled with the drain of the first P-type transistor; and a second N-type transistor comprising a drain coupled with a source of the first N-type transistor, wherein a gate of the first P-type transistor is configured to receive the clock signal; a gate of the first N-type transistor is configured to receive one of the clock signal and the first latch output signal; and a gate of the second N-type transistor is configured to receive the other one of the clock signal and the first latch output signal.
 9. The flip-flop circuit of claim 1, further comprising an input stage coupled with the first latch, the input stage being configured to output the first latch input signal based on one of a plurality of input signals.
 10. The flip-flop circuit of claim 1, wherein the first latch is configured to update a logical state of the first latch output signal based on the first latch input signal in response to a first state of the clock signal; and hold the logical state of the first latch output signal in response to a second state of the clock signal, the first state and the second state of the clock signal being logically complementary to each other; and the second latch is configured to update a logical state of the second latch output signal based on the second latch input signal in response to the second state of the clock signal; and hold the logical state of the second latch output signal in response to the first state of the clock signal.
 11. The flip-flop circuit of claim 1, wherein the first latch comprises an AND-OR-INV compound logic gate; and the second latch comprises an OR-AND-INV compound logic gate.
 12. A flip-flop circuit, comprising: a first latch configured to, based on a first signal and in response to a clock signal, generate a second signal; a trigger stage coupled with the first latch and configured to generate a third signal based on the clock signal, the second signal, and a fourth signal; and a second latch coupled with the trigger stage and configured to, based on the third signal and in response to the clock signal, generate the fourth signal, the trigger stage comprising: a voltage setting circuit comprising an output node and configured to set a voltage at the output node of the voltage setting circuit in response to the fourth signal; and a logic gate circuit having a power node electrically coupled with the output node of the voltage setting circuit.
 13. The flip-flop circuit of claim 12, wherein the voltage setting circuit further comprises: a power supply node configured to carry a first supply voltage having the first power supply voltage level; a P-type transistor having a source coupled with the power supply node, a gate configured to receive the fourth signal, and a drain coupled with the output node of the voltage setting circuit; and an N P-type transistor having a drain coupled with the power supply node, a gate configured to receive the fourth signal, and a source coupled with the output node of the voltage setting circuit.
 14. The flip-flop circuit of claim 12, wherein the voltage setting circuit further comprises: a power supply node configured to carry a first supply voltage having the first power supply voltage level; a P-type transistor having a source coupled with the power supply node, a gate configured to receive the fourth signal, and a drain coupled with the output node of the voltage setting circuit; and a diode having an anode coupled with the power supply node and a cathode coupled with the output node of the voltage setting circuit.
 15. The flip-flop circuit of claim 12, wherein the voltage setting circuit further comprises: a first power supply node configured to carry a first supply voltage having the first power supply voltage level; a second power supply node configured to carry a second supply voltage having the second power supply voltage level; a first switching device configured to electrically couple the first power supply node to the output node of the voltage setting circuit in response to the first logical state of the fourth signal and to electrically decouple the first power supply node from the output node of the voltage setting circuit in response to the second state of the fourth signal; and a second switching device configured to electrically couple the second power supply node to the output node of the voltage setting circuit in response to the second logical state of the fourth signal and to electrically decouple the second power supply node from the output node of the voltage setting circuit in response to the first state of the fourth signal.
 16. The flip-flop circuit of claim 12, wherein the first latch comprises: an AND-OR-INV compound logic gate, comprising: a first AND input configured to receive the third signal; a second AND input configured to receive the first signal; a third AND input configured to receive the clock signal; a fourth AND input; and an NOR output configured to carry the second signal; and an inverter, comprising: an input coupled with the NOR output of the AND-OR-INV compound logic gate; and an output coupled with the fourth AND input of the AND-OR-INV compound logic gate.
 17. The flip-flop circuit of claim 12, wherein the second latch comprises: an OR-AND-INV compound logic gate, comprising: a first OR input; a second OR input configured to receive the clock signal; a first NAND input configured to receive the third signal; an NAND output configured to carry the fourth signal; and an inverter, comprising: an input coupled with the NAND output of the OR-AND-INV compound logic gate; and an output coupled with the first OR input of the OR-AND-INV compound logic gate.
 18. A method of operating a flip-flop circuit, the method comprising: setting, by a first latch of the flip-flop circuit based on a first signal and in response to a clock signal, a second signal; setting, by a second latch of the flip-flop circuit based on a third signal by and in response to the clock signal, a fourth signal; and generating the third signal by a trigger circuit based on the second signal, the generating the third signal comprising setting the trigger circuit to cause the third signal to have different voltage swings based on the fourth signal and the second signal.
 19. The method of claim 18, wherein the generating the third signal comprises causing the third signal to have: a first voltage swing in response to a first state of the fourth signal; and a second voltage swing in response to a second state of the fourth signal, the second voltage swing being less than the first voltage swing.
 20. The method of claim 18, wherein the setting the trigger circuit comprises: setting a voltage at an output node of a voltage setting circuit of the trigger circuit to have a first power supply voltage level in response to the first state of the fourth signal and a second power supply voltage level in response to the second state of the fourth signal, the second power supply voltage level being less than the first power supply voltage level. 